This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to new structures and fabrication methods for integrated circuits that use advanced materials.
As integrated circuits have become increasingly smaller, electrically conductive structures within the integrated circuits are placed increasingly closer together. This situation tends to enhance the inherent problem of parasitic capacitance between adjacent electrically conductive structures. Thus, new electrically insulating materials have been devised for use between electrically conductive structures, to reduce such capacitance problems. The new electrically insulating materials typically have lower dielectric constants, and thus are generally referred to as low k materials. While low k materials help to resolve the capacitance problems described above, they unfortunately tend to introduce new challenges.
Low k materials are typically filled with small voids that help reduce the material""s effective dielectric constant. Thus, there is less of the material itself within a given volume, which tends to reduce the structural strength of the material. The resulting porous and brittle nature of such low k materials presents new challenges in both the fabrication and packaging processes. Unless special precautions are taken, the robustness and reliability of an integrated circuit that is fabricated with low k materials may be reduced from that of an integrated circuit that is fabricated with traditional materials, because low k materials differ from traditional materials in properties such as thermal coefficient of expansion, moisture absorption, adhesion to adjacent layers, mechanical strength, and thermal conductivity.
Concerning the problem of thermal coefficient of expansion, when adjacent layers having different thermal coefficients of expansion are heated and cooled, such as occurs during the normal operation of an integrated circuit, the layers tend to expand and contract at different rates and to different degrees. These forces induce strains in the adjacent and proximal layers. Low k materials tend to have thermal coefficients of expansion that are sufficiently different from those of the other materials used to fabricate integrated circuits that such strains create problems, which may be both physical and electrical, in the integrated circuit.
As to the problem of moisture absorption, the porosity of low k materials makes them susceptible to absorbing the moisture that typically tends to diffuse into the packaged integrated circuit. As the low k material absorbs such moisture, the properties of the low k material changes. For example, the dielectric constant of the material changes, because the voids tend to fill with water or water vapor. The moisture in the voids may rapidly expand during subsequent heating operations such as baking or solder ball reflow, causing the layers of the integrated circuit to burst apart, resulting in dramatic device failure. The moisture absorbed by the low k material also tends to cause other problems, some of which are described in more detail below.
Integrated circuits containing low k materials are inherently more prone to delamination, either between the various layers of the integrated circuit itself, or between the integrated circuit and packaging materials, such as underfill and mold compound, or other materials which are in intimate contact with the integrated circuit. There are several probable causes for such delamination, including a reduction in the adhesion of a low k layer due to absorption of moisture, as described above. In addition, because the low k material tends to be very porous by nature, there is physically less material available to form adhesive bonds with adjacent layers. Further, the strains induced by differing thermal coefficients of expansion also tend to shear the low k layer from adjacent layers, which again tends to enhance the occurrence of delamination.
As to mechanical strength, low k materials are typically more brittle and have a lower breaking point than other materials. One reason for this is, again, the porosity of the low k material, where a significant percentage of its physical volume is filled with voids. Thus, integrated circuits containing low k materials are inherently more prone to breaking or cracking during processes where physical contact is made with the integrated circuit surface, such as wire bonding and electrical probing, or processes that cause bending stresses such as mold curing, underfill curing, solder ball reflow, or temperature cycling.
Finally, because of their porosity and other properties, low k materials tend to be very poor thermal conductors, typically much less than half a watt per meter-Kelvin (W/mK). This contrasts significantly with the thermal conductivity of traditional integrated circuit and packaging materials such as silicon (60-90 W/mK), copper (380-390 W/mK), mold compound (0.7-2 W/mK), or die attach material (2-4 W/mK). Thus, the thermal energy created during the normal operation of the integrated circuit tends to not be dissipated well by low k materials. Therefore, thermal energy tends to build up within the integrated circuit, and is expressed as localized areas of increased temperature, or hot spots.
One example of where the structural weakness of low k materials has been especially detrimental is when they are used as dielectrics under bonding pad structures. When a wire bonding operation is performed, a relatively high degree of force is applied to the bonding pad, which force tends to be transferred down through the bonding pad structure and into underlying structures. When the bonding pad overlies electrical structures, such as input/output cells, the low k materials used for the dielectric layers in such electrical structures tend to crack or delaminate from adjacent layers under the load of the transferred force. This problem could be resolved by moving the input/output cells out from under the bonding pads, but this would tend to increase the size of the integrated circuit, which not desirable.
There is a need, therefore, for new structures, processes, and materials for use in integrated circuit fabrication, which help to alleviate one or more of the challenges that are enhanced by the use of low k materials.
The above and other needs are met by a bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer is disposed immediately under the electrically conductive capping layer, without any intervening layers between the electrically conductive capping layer and the electrically conductive first supporting layer. The electrically conductive first supporting layer is configured as one of a sheet having no voids and a sheet having slotted voids in a first direction. An electrically conductive second supporting layer is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as one of a sheet having slotted voids in the first direction, a sheet having slotted voids in a second direction, and a sheet having checkerboard voids.
In this manner, the first and second supporting layers provide structural support for the layers below the bonding pad structure, such as electrical circuitry like input/output cells. With the supporting layers configured as described herein, pressure that is applied to the bonding pad structure, such as during a wire bonding operation, is absorbed or redirected so that the more delicate structures underneath, including low k dielectric layers, are protected from the force applied during the bonding operation. In this manner, the delicate underlying structures do not suffer physical damage, such as cracks and delamination.
In various preferred embodiments, the bonding pad structure includes an electrically nonconductive layer disposed between the electrically conductive first supporting layer and the electrically conductive second supporting layer. The electrically nonconductive layer is preferably either a low k layer or a silicon oxide layer. Preferably, the electrically conductive capping layer is formed of aluminum. The electrically conductive first supporting layer is preferably formed of copper. The electrically conductive first supporting layer preferably has a thickness of no less than about one micron. Preferably, the electrically conductive second supporting layer is formed of copper. In a preferred embodiment, the first direction is perpendicular to the second direction.
The configuration of the electrically conductive first supporting layer and the electrically conductive second supporting layer has many different combinations. In a first embodiment, the electrically conductive first supporting layer is configured as a sheet having no voids, and the electrically conductive second supporting layer is configured as a sheet having slotted voids in the first direction. In a second embodiment, the electrically conductive first supporting layer is configured as a sheet having no voids, and the electrically conductive second supporting layer is configured as a sheet having slotted voids in a second direction. In a third embodiment, the electrically conductive first supporting layer is configured as a sheet having no voids, and the electrically conductive second supporting layer is configured as a sheet having checkerboard voids.
In a fourth embodiment, the electrically conductive first supporting layer is configured as a sheet having slotted voids in a first direction, and the electrically conductive second supporting layer is configured as a sheet having slotted voids in the first direction. In a fifth embodiment, the electrically conductive first supporting layer is configured as a sheet having slotted voids in a first direction, and the electrically conductive second supporting layer is configured as a sheet having slotted voids in a second direction. In a sixth embodiment, the electrically conductive first supporting layer is configured as a sheet having slotted voids in a first direction, and the electrically conductive second supporting layer is configured as a sheet having checkerboard voids.
Also described is an integrated circuit having the bonding pad structure described herein, and an input/output cell disposed directly underneath and electrically connected to the bonding pad structure. In another embodiment, electrically conductive third layers are disposed under the electrically conductive second supporting layer, and low k layers electrically insulate the electrically conductive third layers from one another and from the electrically conductive second supporting layer.